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DEFINITIONS
This source file includes following definitions.
- GC_test_and_set
- GC_test_and_set
- GC_clear
- GC_test_and_set
- GC_test_and_set
- GC_test_and_set
- GC_test_and_set
- GC_clear
- GC_test_and_set
- GC_clear
- GC_test_and_set
- GC_test_and_set
- GC_test_and_set
- GC_memsync
- GC_test_and_set
- GC_clear
- GC_clear
- GC_compare_and_exchange
- GC_memory_barrier
- GC_compare_and_exchange
- GC_compare_and_exchange
- GC_memory_barrier
- GC_compare_and_exchange
- GC_memory_barrier
- GC_compare_and_exchange
- GC_compare_and_exchange
- GC_memory_barrier
- GC_compare_and_exchange
- GC_atomic_add
1 /*
2 * Copyright 1988, 1989 Hans-J. Boehm, Alan J. Demers
3 * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
4 * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
5 * Copyright (c) 1999 by Hewlett-Packard Company. All rights reserved.
6 *
7 *
8 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
9 * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
10 *
11 * Permission is hereby granted to use or copy this program
12 * for any purpose, provided the above notices are retained on all copies.
13 * Permission to modify the code and to distribute modified code is granted,
14 * provided the above notices are retained, and a notice that the code was
15 * modified is included with the above copyright notice.
16 */
17
18 #ifndef GC_LOCKS_H
19 #define GC_LOCKS_H
20
21 /*
22 * Mutual exclusion between allocator/collector routines.
23 * Needed if there is more than one allocator thread.
24 * FASTLOCK() is assumed to try to acquire the lock in a cheap and
25 * dirty way that is acceptable for a few instructions, e.g. by
26 * inhibiting preemption. This is assumed to have succeeded only
27 * if a subsequent call to FASTLOCK_SUCCEEDED() returns TRUE.
28 * FASTUNLOCK() is called whether or not FASTLOCK_SUCCEEDED().
29 * If signals cannot be tolerated with the FASTLOCK held, then
30 * FASTLOCK should disable signals. The code executed under
31 * FASTLOCK is otherwise immune to interruption, provided it is
32 * not restarted.
33 * DCL_LOCK_STATE declares any local variables needed by LOCK and UNLOCK
34 * and/or DISABLE_SIGNALS and ENABLE_SIGNALS and/or FASTLOCK.
35 * (There is currently no equivalent for FASTLOCK.)
36 *
37 * In the PARALLEL_MARK case, we also need to define a number of
38 * other inline finctions here:
39 * GC_bool GC_compare_and_exchange( volatile GC_word *addr,
40 * GC_word old, GC_word new )
41 * GC_word GC_atomic_add( volatile GC_word *addr, GC_word how_much )
42 * void GC_memory_barrier( )
43 *
44 */
45 # ifdef THREADS
46 void GC_noop1 GC_PROTO((word));
47 # ifdef PCR_OBSOLETE /* Faster, but broken with multiple lwp's */
48 # include "th/PCR_Th.h"
49 # include "th/PCR_ThCrSec.h"
50 extern struct PCR_Th_MLRep GC_allocate_ml;
51 # define DCL_LOCK_STATE PCR_sigset_t GC_old_sig_mask
52 # define LOCK() PCR_Th_ML_Acquire(&GC_allocate_ml)
53 # define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
54 # define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
55 # define FASTLOCK() PCR_ThCrSec_EnterSys()
56 /* Here we cheat (a lot): */
57 # define FASTLOCK_SUCCEEDED() (*(int *)(&GC_allocate_ml) == 0)
58 /* TRUE if nobody currently holds the lock */
59 # define FASTUNLOCK() PCR_ThCrSec_ExitSys()
60 # endif
61 # ifdef PCR
62 # include <base/PCR_Base.h>
63 # include <th/PCR_Th.h>
64 extern PCR_Th_ML GC_allocate_ml;
65 # define DCL_LOCK_STATE \
66 PCR_ERes GC_fastLockRes; PCR_sigset_t GC_old_sig_mask
67 # define LOCK() PCR_Th_ML_Acquire(&GC_allocate_ml)
68 # define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
69 # define FASTLOCK() (GC_fastLockRes = PCR_Th_ML_Try(&GC_allocate_ml))
70 # define FASTLOCK_SUCCEEDED() (GC_fastLockRes == PCR_ERes_okay)
71 # define FASTUNLOCK() {\
72 if( FASTLOCK_SUCCEEDED() ) PCR_Th_ML_Release(&GC_allocate_ml); }
73 # endif
74 # ifdef SRC_M3
75 extern GC_word RT0u__inCritical;
76 # define LOCK() RT0u__inCritical++
77 # define UNLOCK() RT0u__inCritical--
78 # endif
79 # ifdef GC_SOLARIS_THREADS
80 # include <thread.h>
81 # include <signal.h>
82 extern mutex_t GC_allocate_ml;
83 # define LOCK() mutex_lock(&GC_allocate_ml);
84 # define UNLOCK() mutex_unlock(&GC_allocate_ml);
85 # endif
86
87 /* Try to define GC_TEST_AND_SET and a matching GC_CLEAR for spin lock */
88 /* acquisition and release. We need this for correct operation of the */
89 /* incremental GC. */
90 # ifdef __GNUC__
91 # if defined(I386)
92 inline static int GC_test_and_set(volatile unsigned int *addr) {
93 int oldval;
94 /* Note: the "xchg" instruction does not need a "lock" prefix */
95 __asm__ __volatile__("xchgl %0, %1"
96 : "=r"(oldval), "=m"(*(addr))
97 : "0"(1), "m"(*(addr)) : "memory");
98 return oldval;
99 }
100 # define GC_TEST_AND_SET_DEFINED
101 # endif
102 # if defined(IA64)
103 # if defined(__INTEL_COMPILER)
104 # include <ia64intrin.h>
105 # endif
106 inline static int GC_test_and_set(volatile unsigned int *addr) {
107 long oldval, n = 1;
108 # ifndef __INTEL_COMPILER
109 __asm__ __volatile__("xchg4 %0=%1,%2"
110 : "=r"(oldval), "=m"(*addr)
111 : "r"(n), "1"(*addr) : "memory");
112 # else
113 oldval = _InterlockedExchange(addr, n);
114 # endif
115 return oldval;
116 }
117 # define GC_TEST_AND_SET_DEFINED
118 /* Should this handle post-increment addressing?? */
119 inline static void GC_clear(volatile unsigned int *addr) {
120 # ifndef __INTEL_COMPILER
121 __asm__ __volatile__("st4.rel %0=r0" : "=m" (*addr) : : "memory");
122 # else
123 // there is no st4 but I can use xchg I hope
124 _InterlockedExchange(addr, 0);
125 # endif
126 }
127 # define GC_CLEAR_DEFINED
128 # endif
129 # ifdef SPARC
130 inline static int GC_test_and_set(volatile unsigned int *addr) {
131 int oldval;
132
133 __asm__ __volatile__("ldstub %1,%0"
134 : "=r"(oldval), "=m"(*addr)
135 : "m"(*addr) : "memory");
136 return oldval;
137 }
138 # define GC_TEST_AND_SET_DEFINED
139 # endif
140 # ifdef M68K
141 /* Contributed by Tony Mantler. I'm not sure how well it was */
142 /* tested. */
143 inline static int GC_test_and_set(volatile unsigned int *addr) {
144 char oldval; /* this must be no longer than 8 bits */
145
146 /* The return value is semi-phony. */
147 /* 'tas' sets bit 7 while the return */
148 /* value pretends bit 0 was set */
149 __asm__ __volatile__(
150 "tas %1@; sne %0; negb %0"
151 : "=d" (oldval)
152 : "a" (addr) : "memory");
153 return oldval;
154 }
155 # define GC_TEST_AND_SET_DEFINED
156 # endif
157 # if defined(POWERPC)
158 # if CPP_WORDSZ == 64
159 inline static int GC_test_and_set(volatile unsigned int *addr) {
160 unsigned long oldval;
161 unsigned long temp = 1; /* locked value */
162
163 __asm__ __volatile__(
164 "1:\tldarx %0,0,%3\n" /* load and reserve */
165 "\tcmpdi %0, 0\n" /* if load is */
166 "\tbne 2f\n" /* non-zero, return already set */
167 "\tstdcx. %2,0,%1\n" /* else store conditional */
168 "\tbne- 1b\n" /* retry if lost reservation */
169 "\tsync\n" /* import barrier */
170 "2:\t\n" /* oldval is zero if we set */
171 : "=&r"(oldval), "=p"(addr)
172 : "r"(temp), "1"(addr)
173 : "cr0","memory");
174 return (int)oldval;
175 }
176 # else
177 inline static int GC_test_and_set(volatile unsigned int *addr) {
178 int oldval;
179 int temp = 1; /* locked value */
180
181 __asm__ __volatile__(
182 "1:\tlwarx %0,0,%3\n" /* load and reserve */
183 "\tcmpwi %0, 0\n" /* if load is */
184 "\tbne 2f\n" /* non-zero, return already set */
185 "\tstwcx. %2,0,%1\n" /* else store conditional */
186 "\tbne- 1b\n" /* retry if lost reservation */
187 "\tsync\n" /* import barrier */
188 "2:\t\n" /* oldval is zero if we set */
189 : "=&r"(oldval), "=p"(addr)
190 : "r"(temp), "1"(addr)
191 : "cr0","memory");
192 return oldval;
193 }
194 # endif
195 # define GC_TEST_AND_SET_DEFINED
196 inline static void GC_clear(volatile unsigned int *addr) {
197 __asm__ __volatile__("lwsync" : : : "memory");
198 *(addr) = 0;
199 }
200 # define GC_CLEAR_DEFINED
201 # endif
202 # if defined(ALPHA)
203 inline static int GC_test_and_set(volatile unsigned int * addr)
204 {
205 unsigned long oldvalue;
206 unsigned long temp;
207
208 __asm__ __volatile__(
209 "1: ldl_l %0,%1\n"
210 " and %0,%3,%2\n"
211 " bne %2,2f\n"
212 " xor %0,%3,%0\n"
213 " stl_c %0,%1\n"
214 # ifdef __ELF__
215 " beq %0,3f\n"
216 # else
217 " beq %0,1b\n"
218 # endif
219 " mb\n"
220 "2:\n"
221 # ifdef __ELF__
222 ".section .text2,\"ax\"\n"
223 "3: br 1b\n"
224 ".previous"
225 # endif
226 :"=&r" (temp), "=m" (*addr), "=&r" (oldvalue)
227 :"Ir" (1), "m" (*addr)
228 :"memory");
229
230 return oldvalue;
231 }
232 # define GC_TEST_AND_SET_DEFINED
233 inline static void GC_clear(volatile unsigned int *addr) {
234 __asm__ __volatile__("mb" : : : "memory");
235 *(addr) = 0;
236 }
237 # define GC_CLEAR_DEFINED
238 # endif /* ALPHA */
239 # ifdef ARM32
240 inline static int GC_test_and_set(volatile unsigned int *addr) {
241 int oldval;
242 /* SWP on ARM is very similar to XCHG on x86. Doesn't lock the
243 * bus because there are no SMP ARM machines. If/when there are,
244 * this code will likely need to be updated. */
245 /* See linuxthreads/sysdeps/arm/pt-machine.h in glibc-2.1 */
246 __asm__ __volatile__("swp %0, %1, [%2]"
247 : "=r"(oldval)
248 : "r"(1), "r"(addr)
249 : "memory");
250 return oldval;
251 }
252 # define GC_TEST_AND_SET_DEFINED
253 # endif /* ARM32 */
254 # ifdef CRIS
255 inline static int GC_test_and_set(volatile unsigned int *addr) {
256 /* Ripped from linuxthreads/sysdeps/cris/pt-machine.h. */
257 /* Included with Hans-Peter Nilsson's permission. */
258 register unsigned long int ret;
259
260 /* Note the use of a dummy output of *addr to expose the write.
261 * The memory barrier is to stop *other* writes being moved past
262 * this code.
263 */
264 __asm__ __volatile__("clearf\n"
265 "0:\n\t"
266 "movu.b [%2],%0\n\t"
267 "ax\n\t"
268 "move.b %3,[%2]\n\t"
269 "bwf 0b\n\t"
270 "clearf"
271 : "=&r" (ret), "=m" (*addr)
272 : "r" (addr), "r" ((int) 1), "m" (*addr)
273 : "memory");
274 return ret;
275 }
276 # define GC_TEST_AND_SET_DEFINED
277 # endif /* CRIS */
278 # ifdef S390
279 inline static int GC_test_and_set(volatile unsigned int *addr) {
280 int ret;
281 __asm__ __volatile__ (
282 " l %0,0(%2)\n"
283 "0: cs %0,%1,0(%2)\n"
284 " jl 0b"
285 : "=&d" (ret)
286 : "d" (1), "a" (addr)
287 : "cc", "memory");
288 return ret;
289 }
290 # endif
291 # endif /* __GNUC__ */
292 # if (defined(ALPHA) && !defined(__GNUC__))
293 # ifndef OSF1
294 --> We currently assume that if gcc is not used, we are
295 --> running under Tru64.
296 # endif
297 # include <machine/builtins.h>
298 # include <c_asm.h>
299 # define GC_test_and_set(addr) __ATOMIC_EXCH_LONG(addr, 1)
300 # define GC_TEST_AND_SET_DEFINED
301 # define GC_clear(addr) { asm("mb"); *(volatile unsigned *)addr = 0; }
302 # define GC_CLEAR_DEFINED
303 # endif
304 # if defined(MSWIN32)
305 # define GC_test_and_set(addr) InterlockedExchange((LPLONG)addr,1)
306 # define GC_TEST_AND_SET_DEFINED
307 # endif
308 # ifdef MIPS
309 # ifdef LINUX
310 # include <sys/tas.h>
311 # define GC_test_and_set(addr) _test_and_set((int *) addr,1)
312 # define GC_TEST_AND_SET_DEFINED
313 # elif __mips < 3 || !(defined (_ABIN32) || defined(_ABI64)) \
314 || !defined(_COMPILER_VERSION) || _COMPILER_VERSION < 700
315 # ifdef __GNUC__
316 # define GC_test_and_set(addr) _test_and_set((void *)addr,1)
317 # else
318 # define GC_test_and_set(addr) test_and_set((void *)addr,1)
319 # endif
320 # else
321 # include <sgidefs.h>
322 # include <mutex.h>
323 # define GC_test_and_set(addr) __test_and_set32((void *)addr,1)
324 # define GC_clear(addr) __lock_release(addr);
325 # define GC_CLEAR_DEFINED
326 # endif
327 # define GC_TEST_AND_SET_DEFINED
328 # endif /* MIPS */
329 # if defined(_AIX)
330 # include <sys/atomic_op.h>
331 # if (defined(_POWER) || defined(_POWERPC))
332 # if defined(__GNUC__)
333 inline static void GC_memsync() {
334 __asm__ __volatile__ ("sync" : : : "memory");
335 }
336 # else
337 # ifndef inline
338 # define inline __inline
339 # endif
340 # pragma mc_func GC_memsync { \
341 "7c0004ac" /* sync (same opcode used for dcs)*/ \
342 }
343 # endif
344 # else
345 # error dont know how to memsync
346 # endif
347 inline static int GC_test_and_set(volatile unsigned int * addr) {
348 int oldvalue = 0;
349 if (compare_and_swap((void *)addr, &oldvalue, 1)) {
350 GC_memsync();
351 return 0;
352 } else return 1;
353 }
354 # define GC_TEST_AND_SET_DEFINED
355 inline static void GC_clear(volatile unsigned int *addr) {
356 GC_memsync();
357 *(addr) = 0;
358 }
359 # define GC_CLEAR_DEFINED
360
361 # endif
362 # if 0 /* defined(HP_PA) */
363 /* The official recommendation seems to be to not use ldcw from */
364 /* user mode. Since multithreaded incremental collection doesn't */
365 /* work anyway on HP_PA, this shouldn't be a major loss. */
366
367 /* "set" means 0 and "clear" means 1 here. */
368 # define GC_test_and_set(addr) !GC_test_and_clear(addr);
369 # define GC_TEST_AND_SET_DEFINED
370 # define GC_clear(addr) GC_noop1((word)(addr)); *(volatile unsigned int *)addr = 1;
371 /* The above needs a memory barrier! */
372 # define GC_CLEAR_DEFINED
373 # endif
374 # if defined(GC_TEST_AND_SET_DEFINED) && !defined(GC_CLEAR_DEFINED)
375 # ifdef __GNUC__
376 inline static void GC_clear(volatile unsigned int *addr) {
377 /* Try to discourage gcc from moving anything past this. */
378 __asm__ __volatile__(" " : : : "memory");
379 *(addr) = 0;
380 }
381 # else
382 /* The function call in the following should prevent the */
383 /* compiler from moving assignments to below the UNLOCK. */
384 # define GC_clear(addr) GC_noop1((word)(addr)); \
385 *((volatile unsigned int *)(addr)) = 0;
386 # endif
387 # define GC_CLEAR_DEFINED
388 # endif /* !GC_CLEAR_DEFINED */
389
390 # if !defined(GC_TEST_AND_SET_DEFINED)
391 # define USE_PTHREAD_LOCKS
392 # endif
393
394 # if defined(GC_PTHREADS) && !defined(GC_SOLARIS_THREADS) \
395 && !defined(GC_WIN32_THREADS)
396 # define NO_THREAD (pthread_t)(-1)
397 # include <pthread.h>
398 # if defined(PARALLEL_MARK)
399 /* We need compare-and-swap to update mark bits, where it's */
400 /* performance critical. If USE_MARK_BYTES is defined, it is */
401 /* no longer needed for this purpose. However we use it in */
402 /* either case to implement atomic fetch-and-add, though that's */
403 /* less performance critical, and could perhaps be done with */
404 /* a lock. */
405 # if defined(GENERIC_COMPARE_AND_SWAP)
406 /* Probably not useful, except for debugging. */
407 /* We do use GENERIC_COMPARE_AND_SWAP on PA_RISC, but we */
408 /* minimize its use. */
409 extern pthread_mutex_t GC_compare_and_swap_lock;
410
411 /* Note that if GC_word updates are not atomic, a concurrent */
412 /* reader should acquire GC_compare_and_swap_lock. On */
413 /* currently supported platforms, such updates are atomic. */
414 extern GC_bool GC_compare_and_exchange(volatile GC_word *addr,
415 GC_word old, GC_word new_val);
416 # endif /* GENERIC_COMPARE_AND_SWAP */
417 # if defined(I386)
418 # if !defined(GENERIC_COMPARE_AND_SWAP)
419 /* Returns TRUE if the comparison succeeded. */
420 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
421 GC_word old,
422 GC_word new_val)
423 {
424 char result;
425 __asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1"
426 : "+m"(*(addr)), "=r"(result)
427 : "r" (new_val), "a"(old) : "memory");
428 return (GC_bool) result;
429 }
430 # endif /* !GENERIC_COMPARE_AND_SWAP */
431 inline static void GC_memory_barrier()
432 {
433 /* We believe the processor ensures at least processor */
434 /* consistent ordering. Thus a compiler barrier */
435 /* should suffice. */
436 __asm__ __volatile__("" : : : "memory");
437 }
438 # endif /* I386 */
439
440 # if defined(POWERPC)
441 # if !defined(GENERIC_COMPARE_AND_SWAP)
442 # if CPP_WORDSZ == 64
443 /* Returns TRUE if the comparison succeeded. */
444 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
445 GC_word old, GC_word new_val)
446 {
447 unsigned long result, dummy;
448 __asm__ __volatile__(
449 "1:\tldarx %0,0,%5\n"
450 "\tcmpd %0,%4\n"
451 "\tbne 2f\n"
452 "\tstdcx. %3,0,%2\n"
453 "\tbne- 1b\n"
454 "\tsync\n"
455 "\tli %1, 1\n"
456 "\tb 3f\n"
457 "2:\tli %1, 0\n"
458 "3:\t\n"
459 : "=&r" (dummy), "=r" (result), "=p" (addr)
460 : "r" (new_val), "r" (old), "2"(addr)
461 : "cr0","memory");
462 return (GC_bool) result;
463 }
464 # else
465 /* Returns TRUE if the comparison succeeded. */
466 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
467 GC_word old, GC_word new_val)
468 {
469 int result, dummy;
470 __asm__ __volatile__(
471 "1:\tlwarx %0,0,%5\n"
472 "\tcmpw %0,%4\n"
473 "\tbne 2f\n"
474 "\tstwcx. %3,0,%2\n"
475 "\tbne- 1b\n"
476 "\tsync\n"
477 "\tli %1, 1\n"
478 "\tb 3f\n"
479 "2:\tli %1, 0\n"
480 "3:\t\n"
481 : "=&r" (dummy), "=r" (result), "=p" (addr)
482 : "r" (new_val), "r" (old), "2"(addr)
483 : "cr0","memory");
484 return (GC_bool) result;
485 }
486 # endif
487 # endif /* !GENERIC_COMPARE_AND_SWAP */
488 inline static void GC_memory_barrier()
489 {
490 __asm__ __volatile__("sync" : : : "memory");
491 }
492 # endif /* POWERPC */
493
494 # if defined(IA64)
495 # if !defined(GENERIC_COMPARE_AND_SWAP)
496 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
497 GC_word old, GC_word new_val)
498 {
499 unsigned long oldval;
500 # if CPP_WORDSZ == 32
501 __asm__ __volatile__(
502 "addp4 %0=0,%1\n"
503 "mov ar.ccv=%3 ;; cmpxchg4.rel %0=[%0],%2,ar.ccv"
504 : "=&r"(oldval)
505 : "r"(addr), "r"(new_val), "r"(old) : "memory");
506 # else
507 __asm__ __volatile__(
508 "mov ar.ccv=%3 ;; cmpxchg8.rel %0=[%1],%2,ar.ccv"
509 : "=r"(oldval)
510 : "r"(addr), "r"(new_val), "r"(old) : "memory");
511 # endif
512 return (oldval == old);
513 }
514 # endif /* !GENERIC_COMPARE_AND_SWAP */
515 # if 0
516 /* Shouldn't be needed; we use volatile stores instead. */
517 inline static void GC_memory_barrier()
518 {
519 __asm__ __volatile__("mf" : : : "memory");
520 }
521 # endif /* 0 */
522 # endif /* IA64 */
523 # if defined(ALPHA)
524 # if !defined(GENERIC_COMPARE_AND_SWAP)
525 # if defined(__GNUC__)
526 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
527 GC_word old, GC_word new_val)
528 {
529 unsigned long was_equal;
530 unsigned long temp;
531
532 __asm__ __volatile__(
533 "1: ldq_l %0,%1\n"
534 " cmpeq %0,%4,%2\n"
535 " mov %3,%0\n"
536 " beq %2,2f\n"
537 " stq_c %0,%1\n"
538 " beq %0,1b\n"
539 "2:\n"
540 " mb\n"
541 :"=&r" (temp), "=m" (*addr), "=&r" (was_equal)
542 : "r" (new_val), "Ir" (old)
543 :"memory");
544 return was_equal;
545 }
546 # else /* !__GNUC__ */
547 inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
548 GC_word old, GC_word new_val)
549 {
550 return __CMP_STORE_QUAD(addr, old, new_val, addr);
551 }
552 # endif /* !__GNUC__ */
553 # endif /* !GENERIC_COMPARE_AND_SWAP */
554 # ifdef __GNUC__
555 inline static void GC_memory_barrier()
556 {
557 __asm__ __volatile__("mb" : : : "memory");
558 }
559 # else
560 # define GC_memory_barrier() asm("mb")
561 # endif /* !__GNUC__ */
562 # endif /* ALPHA */
563 # if defined(S390)
564 # if !defined(GENERIC_COMPARE_AND_SWAP)
565 inline static GC_bool GC_compare_and_exchange(volatile C_word *addr,
566 GC_word old, GC_word new_val)
567 {
568 int retval;
569 __asm__ __volatile__ (
570 # ifndef __s390x__
571 " cs %1,%2,0(%3)\n"
572 # else
573 " csg %1,%2,0(%3)\n"
574 # endif
575 " ipm %0\n"
576 " srl %0,28\n"
577 : "=&d" (retval), "+d" (old)
578 : "d" (new_val), "a" (addr)
579 : "cc", "memory");
580 return retval == 0;
581 }
582 # endif
583 # endif
584 # if !defined(GENERIC_COMPARE_AND_SWAP)
585 /* Returns the original value of *addr. */
586 inline static GC_word GC_atomic_add(volatile GC_word *addr,
587 GC_word how_much)
588 {
589 GC_word old;
590 do {
591 old = *addr;
592 } while (!GC_compare_and_exchange(addr, old, old+how_much));
593 return old;
594 }
595 # else /* GENERIC_COMPARE_AND_SWAP */
596 /* So long as a GC_word can be atomically updated, it should */
597 /* be OK to read *addr without a lock. */
598 extern GC_word GC_atomic_add(volatile GC_word *addr, GC_word how_much);
599 # endif /* GENERIC_COMPARE_AND_SWAP */
600
601 # endif /* PARALLEL_MARK */
602
603 # if !defined(THREAD_LOCAL_ALLOC) && !defined(USE_PTHREAD_LOCKS)
604 /* In the THREAD_LOCAL_ALLOC case, the allocation lock tends to */
605 /* be held for long periods, if it is held at all. Thus spinning */
606 /* and sleeping for fixed periods are likely to result in */
607 /* significant wasted time. We thus rely mostly on queued locks. */
608 # define USE_SPIN_LOCK
609 extern volatile unsigned int GC_allocate_lock;
610 extern void GC_lock(void);
611 /* Allocation lock holder. Only set if acquired by client through */
612 /* GC_call_with_alloc_lock. */
613 # ifdef GC_ASSERTIONS
614 # define LOCK() \
615 { if (GC_test_and_set(&GC_allocate_lock)) GC_lock(); \
616 SET_LOCK_HOLDER(); }
617 # define UNLOCK() \
618 { GC_ASSERT(I_HOLD_LOCK()); UNSET_LOCK_HOLDER(); \
619 GC_clear(&GC_allocate_lock); }
620 # else
621 # define LOCK() \
622 { if (GC_test_and_set(&GC_allocate_lock)) GC_lock(); }
623 # define UNLOCK() \
624 GC_clear(&GC_allocate_lock)
625 # endif /* !GC_ASSERTIONS */
626 # if 0
627 /* Another alternative for OSF1 might be: */
628 # include <sys/mman.h>
629 extern msemaphore GC_allocate_semaphore;
630 # define LOCK() { if (msem_lock(&GC_allocate_semaphore, MSEM_IF_NOWAIT) \
631 != 0) GC_lock(); else GC_allocate_lock = 1; }
632 /* The following is INCORRECT, since the memory model is too weak. */
633 /* Is this true? Presumably msem_unlock has the right semantics? */
634 /* - HB */
635 # define UNLOCK() { GC_allocate_lock = 0; \
636 msem_unlock(&GC_allocate_semaphore, 0); }
637 # endif /* 0 */
638 # else /* THREAD_LOCAL_ALLOC || USE_PTHREAD_LOCKS */
639 # ifndef USE_PTHREAD_LOCKS
640 # define USE_PTHREAD_LOCKS
641 # endif
642 # endif /* THREAD_LOCAL_ALLOC */
643 # ifdef USE_PTHREAD_LOCKS
644 # include <pthread.h>
645 extern pthread_mutex_t GC_allocate_ml;
646 # ifdef GC_ASSERTIONS
647 # define LOCK() \
648 { GC_lock(); \
649 SET_LOCK_HOLDER(); }
650 # define UNLOCK() \
651 { GC_ASSERT(I_HOLD_LOCK()); UNSET_LOCK_HOLDER(); \
652 pthread_mutex_unlock(&GC_allocate_ml); }
653 # else /* !GC_ASSERTIONS */
654 # if defined(NO_PTHREAD_TRYLOCK)
655 # define LOCK() GC_lock();
656 # else /* !defined(NO_PTHREAD_TRYLOCK) */
657 # define LOCK() \
658 { if (0 != pthread_mutex_trylock(&GC_allocate_ml)) GC_lock(); }
659 # endif
660 # define UNLOCK() pthread_mutex_unlock(&GC_allocate_ml)
661 # endif /* !GC_ASSERTIONS */
662 # endif /* USE_PTHREAD_LOCKS */
663 # define SET_LOCK_HOLDER() GC_lock_holder = pthread_self()
664 # define UNSET_LOCK_HOLDER() GC_lock_holder = NO_THREAD
665 # define I_HOLD_LOCK() (pthread_equal(GC_lock_holder, pthread_self()))
666 extern VOLATILE GC_bool GC_collecting;
667 # define ENTER_GC() GC_collecting = 1;
668 # define EXIT_GC() GC_collecting = 0;
669 extern void GC_lock(void);
670 extern pthread_t GC_lock_holder;
671 # ifdef GC_ASSERTIONS
672 extern pthread_t GC_mark_lock_holder;
673 # endif
674 # endif /* GC_PTHREADS with linux_threads.c implementation */
675 # if defined(GC_WIN32_THREADS)
676 # if defined(GC_PTHREADS)
677 # include <pthread.h>
678 extern pthread_mutex_t GC_allocate_ml;
679 # define LOCK() pthread_mutex_lock(&GC_allocate_ml)
680 # define UNLOCK() pthread_mutex_unlock(&GC_allocate_ml)
681 # else
682 # include <windows.h>
683 GC_API CRITICAL_SECTION GC_allocate_ml;
684 # define LOCK() EnterCriticalSection(&GC_allocate_ml);
685 # define UNLOCK() LeaveCriticalSection(&GC_allocate_ml);
686 # endif
687 # endif
688 # ifndef SET_LOCK_HOLDER
689 # define SET_LOCK_HOLDER()
690 # define UNSET_LOCK_HOLDER()
691 # define I_HOLD_LOCK() FALSE
692 /* Used on platforms were locks can be reacquired, */
693 /* so it doesn't matter if we lie. */
694 # endif
695 # else /* !THREADS */
696 # define LOCK()
697 # define UNLOCK()
698 # endif /* !THREADS */
699 # ifndef SET_LOCK_HOLDER
700 # define SET_LOCK_HOLDER()
701 # define UNSET_LOCK_HOLDER()
702 # define I_HOLD_LOCK() FALSE
703 /* Used on platforms were locks can be reacquired, */
704 /* so it doesn't matter if we lie. */
705 # endif
706 # ifndef ENTER_GC
707 # define ENTER_GC()
708 # define EXIT_GC()
709 # endif
710
711 # ifndef DCL_LOCK_STATE
712 # define DCL_LOCK_STATE
713 # endif
714 # ifndef FASTLOCK
715 # define FASTLOCK() LOCK()
716 # define FASTLOCK_SUCCEEDED() TRUE
717 # define FASTUNLOCK() UNLOCK()
718 # endif
719
720 #endif /* GC_LOCKS_H */